The present invention relates to an improved Domino adder circuit.
Domino adders are the well-known carry-save adders (CAS) which are also often referred to as full adders or 3:2 adders. Domino circuits are a dynamic CMOS (Complementary Metal-Oxide-Semiconductor) circuit which must be controlled by clocks. As known in this art, Domino adders are very suitable for use in pipelined multipliers which are one of the basic building blocks of digital signal processing hardware. A standard Domino adder is schematically shown in FIG. 1. The Domino adder includes a carry evaluating logic 12, a sum evaluating logic 16, a carry generating logic 14, and a sum generating logic 18. The carry evaluating logic 12 includes a PMOS (P-channel Metal-Oxide-Semiconductor) evaluation transistor Q.sub.20, an NMOS (N-channel MOS) pre-discharge transistor Q.sub.21, and three carry evaluating paths connected between the transistors Q.sub.20 and Q.sub.21. The evaluation and pre-discharge transistors Q.sub.20 and Q.sub.21 are controlled by clock .phi.. The three carry evaluating paths are constituted by five PMOS transistors Q.sub.1 through Q.sub.5. The first carry evaluating path is constituted by the transistors Q.sub.1 and Q.sub.3, which are connected in series and controlled by input signals Y and Z respectively. The second carry evaluating path is constituted by the transistors Q.sub.2 and Q.sub.3, which are connected in series and controlled by input signals X and Z respectively. The third carry evaluating path is constituted by the transistors Q.sub.4 and Q.sub.5, which are connected in series and controlled by input signals X and Y respectively. The carry generating logic 14 is controlled by the clock .phi. and a node or carry evaluating point 5 of the carry evaluating logic 12, positioned at the bottom of the carry evaluating paths.
The sum evaluating logic 16 includes a PMOS precharge transistor Q.sub.22, an NMOS evaluation transistor Q.sub.23, and four sum evaluating paths connected between the transistors Q.sub.22 and Q.sub.23 The precharge and evaluation transistors Q.sub.22 and Q.sub.23 are controlled by clock .phi.. The four sum evaluating paths are constituted by seven NMOS transistors Q.sub.6 through Q.sub.2. The first sum evaluating path is constituted by the transistors Q.sub.6 and Q.sub.9 which are connected in series and controlled by input signal Z and node 5 respectively. The second sum evaluating path is constituted by the transistors Q.sub.7 and Q.sub.9, which are connected in series and controlled by input signal Y and node 5 respectively. The third sum evaluating path is constituted by the transistors Q.sub.8 and Q.sub.9, which are connected in series and controlled by input signal X and node 5 respectively. The fourth sum evaluating path is constituted by the transistors Q.sub.10 through Q.sub.12, which are connected in series and controlled by input signals X, Y, and Z respectively. The sum generating logic 18 is controlled by the clock .phi. and a node or sum evaluating point 6 of the sum evaluating logic 16, positioned at the top of the sum evaluating paths.
The operations of the Domino adder include a precharge phase and an evaluation phase. During the precharge phase, clock .phi. is at a low voltage level while clock .phi. is at a high voltage level. Transistors Q.sub.22 and Q.sub.21 are turned on while transistors Q.sub.23 and Q.sub.20 are turned off. The node 5 of the carry evaluating logic 12 is discharged to a low voltage level, i.e. ground (GND), and the node 6 of the sum evaluating logic 16 is precharged to a high voltage level, i.e. the power supply voltage V.sub.cc. During the evaluation phase, clock .phi. is at a high voltage level while clock .phi. is at a low voltage level. Transistors Q.sub.23 and Q.sub.20 are turned on while transistors Q.sub.22 and Q.sub.21 are turned off. The voltage level of node 5 depends on the three input signals X, Y, and Z, and is charged to "HIGH" only if two or all input signals are binary "0". If the node 5 is at level of node 5 depends on the three input signals X, Y, and Z, and is charged to "HIGH" only if two or all input signals are binary "0". If the node 5 is at "HIGH", the output C.sub.o of the carry generating logic 14 is "0", i.e. no carry bit is generated. The node 5 is kept at "LOW" if two or all input signals are binary "1". In such a case, the output C.sub.o of the carry generating logic 14 is "1", i.e. carry is generated. During the evaluation phase, the voltage level of node 6 depends on not only the three input signals X, Y, and Z, but also the state of node 5. If three input signals X, Y, and Z are all "1", the fourth sum evaluating path constituted by transistors Q.sub.10 through Q.sub.12 is "ON", and the node 6 is discharged to ground. Thus, the output S.sub.o of the sum generating logic 18 is " 1". If two input signals are "1" and one is "0", the node 5 is at "LOW" to turn off the transistor Q.sub.9, and the first through fourth sum evaluating paths are all "OFF", so that the node 6 is kept at "HIGH". Thus, the output S.sub.o of the sum generating logic 18 is "0". If one input signal is "1" and two are "0", the node 5 is charged to "HIGH" to turn on the transistor Q.sub.9, and one of the first through third sum evaluating paths is "ON", so that the node 6 is discharged to ground. Thus, the output S.sub.o of the sum generating logic 18 is "1". In this case, the delay time of sum evaluation is the largest case because the sum S.sub.o is correctly generated only after the node 5 of the carry evaluating logic 12 is charged to "HIGH" to turn on the transistor Q.sub.9. If three input signals X, Y, and Z are all "0", all sum evaluating paths are "OFF", so that the node 6 is kept at "HIGH". Thus, the output S.sub.o of the sum generating logic 18 is "0".
As shown in FIG. 1, a standard Domino adder utilizes PMOS transistors Q.sub.1 through Q.sub.5 to constitute the carry evaluating paths. As known in this art, the operation speed of PMOS transistors is two-three times lower than that of NMOS transistors due to the carrier mobility difference. Thus, the PMOS transistors Q.sub.1 through Q.sub.5 significantly affect the carry evaluation speed of Domino adder. Furthermore, since the sum evaluation has to await the carry evaluation in a standard Domino adder, the operation speed of the Domino adder is further lowered.